1. Field of the Invention
This invention relates in general to a process for fabricating storage capacitors for DRAM memory cell units and, in particular, to a process for fabricating storage capacitors for DRAM memory cells having increased electrode surface area for improved capacitance.
2. Description of Related Art
Each of the memory cell units in the cell array of typical DRAM devices includes a MOS transistor and a storage capacitor. FIG. 1 illustrates the schematic diagram of the circuit of a memory cell unit in the DRAM memory array. As is illustrated, a transfer transistor T and a storage capacitor C constitute a basic memory cell unit for a DRAM. The source terminal of the transfer transistor T is connected to a corresponding bit line BL for the memory cell unit in the array, while the drain is connected to one electrode 15 of the storage capacitor C. Gate electrode of the transfer transistor T is strobed by a word line WL of the memory array system. Electrode 14 of storage capacitor C opposite to electrode 15 is connected to a fixed electrical potential of the DRAM system, for example, the ground potential. Sandwiched between the electrodes 15 and 14 of the storage capacitor C is a layer of dielectric material, schematically identified in the drawing by reference numeral 12.
The charging status in the capacitor of a specific memory cell unit represents the data storage in that particular memory location of the DRAM device. In other words, data bits can be stored in the storage capacitor of the memory cell unit utilizing the MOS transistor as the electrical switch to connect the capacitor to the supporting logic circuitry of the device for read-write operations. Sensed presence of electric charges in the storage capacitor can be used to interpret the binary value of the data stored in the cell unit.
Such a DRAM structural configuration, though suitable for mass production of large-scale DRAM memory cell arrays using modern semiconductor fabrication techniques, is constrained by a disadvantageous phenomenon of electric-charge leakage. Inherent characteristics of this basic structural configuration of the circuitry and the material used to implement this circuitry in large scale dictates that electric charges stored in the capacitor suffers leakage. Periodic refreshing operations has to be performed to maintain the charged status in these memory cell units. However, the refreshing operation eats away the available bandwidth of a DRAM device that can be used for normal access to the memory cell units.
There are several available measures to increase the DRAM device duty cycle by reducing the time percentage consumed by refresh operations. Among them are the efforts to increase the storage capacitor capacitance so that larger charge stored can endure longer refreshing cycles. These efforts include the increase of storage capacitor electrode surface area, optimized selection of material used to construct the capacitor dielectric layer, and the reduction of the thickness in the dielectric layer.
FIGS. 2A-2E respectively depict the cross-section views of a conventional DRAM memory cell unit in the process stages of its fabrication. In this depicted prior-art example, hemispherical-grain silicon (HSG-Si) was deployed over the top surface of the bottom electrode for the cell unit storage capacitor as a measure to increase the surface area of the capacitor electrode.
With reference to FIG. 2A, an insulation layer 22 is formed over the surface of the device substrate 20. The cross-sectional view shows that a contact opening is formed in this insulation layer 22 that exposes the surface of a specific source/drain region of the MOS transistor fabricated in the device substrate 20. Note that details of this MOS transistor are not elaborated in this drawing. The insulation layer 22 can be, for example, an interpolysilicon dielectric layer that serves to electrically isolate the MOS transistor with other portions of the other components in the cell unit. An electrically conductive material is then formed to cover the surface of the insulation layer 22, including the exposed surface of the MOS transistor source/drain region. This formed layer 24 may be, for example, a doped polysilicon layer that also fills into the contact opening formed in the insulation layer 22.
Then, as is illustrated in FIG. 2B, the surface of the electrically conductive layer 24 is then covered by an HSG-Si layer 26. This may be achieved by performing a low-pressure chemical vapor deposition (LPCVD) procedure in an SiH.sub.4 - or Si.sub.2 H.sub.6 -containing gaseous environment. The formed HSG-Si layer 26 can then be implanted with impurities in an ion implantation procedure which turns the HSG-Si layer 26 into an electrically conductive material.
In the process of the formation of the HSG-Si layer 26, a layer of native oxide is formed over its surface. Since the existence of such native oxides deteriorates the quality of the electrode for the storage capacitor, therefore a wet etching procedure is then employed to remove this native oxide by submerging the formed native oxide layer in etchants such as an RCA-HF solution. The RCA used may, for example, include NH.sub.4 OH/hot de-ionizing water (HDIW)/H.sub.2 O.sub.2. This process of removing the native oxide layer formed over the surface of the HSG-Si layer, however, has a significant drawback. Due to the fact that the adhesion between the HSG-Si layer 26 and the polysilicon layer 24 directly underneath is not secure, some portions of the HSG-Si layer 26 may well be removed off the surface of the polysilicon layer 24 as a result of the native oxide-removal etching procedure. The etchant solution is thus polluted by the material of the stripped-off HSG-Si, thereby deteriorating the quality of etching to the native oxide layer.
Next, as is illustrated in FIG. 2C, a patterned photoresist layer 28 is then formed over the surface of the HSG-Si layer 26. This photoresist layer 28 covers the designated area of the surface of the HSG-Si layer 26 where the bottom electrode for the storage capacitor is to be formed. Then, subsequently in FIG. 2D, the photoresist layer 28 is employed as the shielding mask for implementing an etching procedure that removes the HSG-Si layer 26 and the conductive layer 24 exposed out of coverage of the masking. After this, the photoresist layer 28 can be removed. The result is the bottom electrode of the storage capacitor, generally identified by the reference numeral 25 in FIG. 2D. This capacitor bottom electrode 25 includes an electrically conductive layer 24a covered by the HSG-Si layer 26a.
Refer next to FIG. 2E, a dielectric material is then formed over the surface of the device substrate forming the dielectric layer 32. The dielectric layer 32 formed may be, for example, consisted of a triple-layered ONO (oxide/nitride/oxide) or a double-layered NO (nitride/oxide) configuration, or, it may be tantalum oxide (Ta.sub.2 O.sub.5). Subsequent fabrication procedural steps can then be employed to shape them into the dielectric and top electrode layers respectively.
Such conventional fabrication process used for the formation of the HSG-Si layer, as mentioned above, suffers its poor adhesion to the underlying polysilicon layer. During the process of removal of the native oxide formed over its top surface, the HSG-Si layer itself may be damaged. Further, the factor of increase to the surface area of the bottom electrode by the employment of the HSG-Si layer is only about 70 percent larger, that is, a factor of about 1.7.times..